The TBPIC16S is a full-featured, single clock cycle and firmware (object) compatible implementation of the industry standard PIC16xxxx family of 8-bit PIC ® microcontrollers. It offers a 4x architectural speedup versus the original devices by requiring only one clock cycle per instruction cycle. It is an efficient and high performance, technology and vendor independent 8-bit microcontroller supplied as a synthesisable IP core.
TBPIC16S is supplied as high quality synthesisable VHDL source code, with full self-checking testbench, example implementation and synthesis scripts, makefiles, documentation, maintenance and support.
TBPIC16S is a standard configuration of our FlexPIC16 configurable microcontroller. It offers the smallest implementation of a PIC code-compatible microcontroller core with the following features:
- Small area requirement (299 slices / 4100 gates*)
- Single phase clock input (up to 46MHz*)
- Single clock per instruction cycle (1 MIP / MHz)
- Built-in support for slow program memories eg. flash
- Code compatibility with original devices
- All 35 instructions implemented
- All instructions except branches execute in a single instruction cycle (up to 46MIPs*)
- All branches execute in two instruction cycles
- Fixed 3 instruction cycles interrupt latency
- RISC-like, Harvard architecture
- Watchdog timer (WDT)
- Low power SLEEP mode with wakeup by interrupt or watchdog timer
- General purpose IO ports with configurable widths(PORTA, PORTB, PORTC)
- Interrupt-on-change feature and provision for programmable pull-ups on PORTB.
- 8-bit counter/timer (TIMER0) with prescaler, externally or internally clocked
- Full interrupt support from peripherals and external interrupt source
- 14-bit instruction, 8-bit data widths
- 8 level hardware stack (max. unlimited)**
- 368 bytes register-file (1K bytes address space)**
- 8K words program memory (max. 64K words)**
* with quoted stack, register-file and program memory sizes, when implemented in a Xilinx Spartan 3AN FPGA. Gate count is for 2-input NAND equivalent gates in ASIC standard cell. Performance is limited to 110MHz (27MIPs) for full IO port output timing compatibility.
** typical sizes quoted, user configurable size to suit application
- Technology and vendor independent
- Suitable for FPGA (Xilinx, Altera, Lattice, Actel etc), ASIC or custom IC implementation.
- High quality parameterised and well commented VHDL RTL source code
- Readily extensible to add additional RAM, peripherals, or other custom interfaces
- Further standard peripherals developed to customer order
- Wide availability of PIC code library routines from multiple sources
- Wide availability of development tools from multiple vendors, including software simulators, assemblers, C-compilers, emulators etc.
PIC is a registered trademark of Microchip Technology Inc.