FlexPIC16 is a fully configurable, efficient and high performance, technology and vendor independent 8-bit microcontroller supplied as a synthesisable IP core. It is software compatible with the industry standard PIC16xxxx family of 8-bit PIC ® microcontrollers.
The FlexPIC16 is supplied as source code with embedded pre-processor directives from which, using the supplied build scripts, a specific configuration of the processor may be automatically generated. The output of the configuration process is clean, structured, commented and fully maintainable VHDL code which may be used for simulation and synthesis in the usual manner.
FlexPIC16 is supplied with a full self-checking testbench, example implementation and synthesis scripts, makefiles, documentation, maintenance and support.
The actual feature set of the configured FlexPIC16 microcontroller depends upon the selected configuration options. The full set of available features is listed here. For details including area and performance of example configurations see the full-featured TBPIC16 or minimal PicoPIC16 pages.
- Code compatibility with original PIC devices*
- Timing compatibility with original PIC devices, including instruction cycle, interrupt latency, general purpose IO port and peripheral timing*
- All 35 instructions implemented
- All instructions except branches execute in a single instruction cycle
- All branches execute in two instruction cycles
- Fixed 3 instruction cycles interrupt latency
- RISC-like, Harvard architecture
- Watchdog timer (WDT)
- Low power SLEEP mode with wakeup by interrupt or watchdog timer
- General purpose IO ports with configurable widths(PORTA, PORTB, PORTC)
- Interrupt-on-change feature and provision for programmable pull-ups on PORTB.
- 8-bit counter/timer (TIMER0) with prescaler, externally or internally clocked
- Full interrupt support from peripherals and external interrupt source
- 14-bit instruction, 8-bit data widths
- Configurable depth hardware stack
- Up to 1K bytes of register-file address space
- Up to 64K words of addressable program memory
* when configured for compatibility and with the required core and peripheral functionality included.
PIC is a registered trademark of Microchip Technology Inc.
- Technology and vendor independent
- Suitable for FPGA (Xilinx, Altera, Lattice, Actel etc), ASIC or custom IC implementation.
- High quality parameterised and well commented VHDL RTL source code
- Readily extensible to add additional RAM, peripherals, or other custom interfaces
- Further standard peripherals developed to customer order
- Wide availability of PIC code library routines from multiple sources
- Wide availability of development tools from multiple vendors, including software simulators, assemblers, C-compilers, emulators etc.
The following architectural features may be configured to be either included or excluded from the generated VHDL source.
- Legacy instructions (TRIS/OPTION)
- IO ports (PORTA/PORTB/PORTC)
- PORTB interrupt-on-change feature
- IOC(B) and WPU(B) register functions
- External interrupt
- Watchdog timer (WDT)
- Sleep functionality
- Various options for compatibility with older PIC devices.
The following configuration options may also be selected so that the generated VHDL suits the intended physical implementation:
- Buffered/unbuffered ClkIn
- Register initialisation in place of explicit nPOR reset signal (eg. for Xilinx FPGAs)
- Synchronous or asynchronous reset
- Synchronous or asynchronous program memory interface
- Xilinx primitives or generic models for memories and clock buffers
- Single or 2-phase internal clocking, the latter for full timing compatibility. (The external clock input, ClkIn, is always single phase.)
Most bus and port widths are configurable upon instantiation by means of VHDL generic ports.
FlexPIC is available to license at cost-effective rates on a royalty-free basis, either for multiple designs, or on a perpetual basis. Please contact us to discuss your requirements.