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FlexPIC16 microcontroller family

Flexibility, configurability, compatibility, performance

  

  

The FlexPIC16 family is a range of efficient and high performance, technology and vendor independent 8-bit microcontrollers supplied as synthesisable IP cores. They are software compatible with the industry standard PIC16xxxx family of 8-bit PIC ® microcontrollers. The family includes four variants, ranging from the full-featured and automatically configurable FlexPIC16, to the minimalist processing-core-only PicoPIC16.

FlexPIC16  

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A full-featured microcontroller core and peripherals, with automated configuration of the code to suit implementation requirements (reset, clocking or memory type for example). Architectural configurations are also automated, for example the inclusion/exclusion of peripherals, instructions and core features.

Most suitable where a range of differing application requirements for multiple applications is envisaged.

  • Automated configuration
  • Configurable implementation
  • Configurable architecture  
  • Maximum flexibility  
  • Processing core and peripherals
  • Code and timing compatibility*
  • Full feature set
  • Up to 4100 gates

TBPIC16S  

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The same full-featured microcontroller core and peripherals as TBPIC16, but with a 4x architectural speed-up and built-in support for slow memories (eg. flash) . The core offers code compatibility with standard PIC microcontrollers.

Most suitable for single or multiple applications requiring a full feature set and with largely fixed architectural requirements.

  • Single clock cycle per instruction cycle (1 MIP / MHz)
  • Built-in support for slow memories
  • Processing core and peripherals
  • Code compatibility
  • Full architectural feature set
  • Standard configuration
  • 4100 gates

TBPIC16  

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A full-featured microcontroller core and peripherals, The core offers code and timing compatibility with standard PIC microcontrollers.

Most suitable for single or multiple applications requiring a full feature set and with largely fixed architectural requirements.

  • Code and timing compatibility
  • Processing core and peripherals
  • Full architectural feature set
  • Standard configuration
  • 0.25 MIP / MHz
  • 3800 gates

PicoPIC16  

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Evaluate it!

  

A minimal implementation including only the processing core, intended for area sensitive applications. This core also features a 4x architectural speed-up versus the original devices. Code compatible with standard PIC microcontrollers.

  • Single clock cycle per instruction cycle (1 MIP / MHz)
  • Processing core only
  • Code compatibility
  • Minimum area  
  • Standard configuration
  • 2000 gates
 * when configured for compatibility and with the required core and peripheral functionality included.

  

  

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